In semiconductor devices, graded regions (e.g., regions with a varying composition of silicon, silicates, metals, etc.) are frequently included adjacent to or as a part of gate elements to decrease device size and increase device performance. The use and effectiveness of these graded regions in devices may be impacted by the composition, scaling, and/or gradation of the graded regions themselves. Traditionally, graded regions (e.g., dielectric materials) may be formed by a high temperature anneal which generates a material concentration variation within the graded region. However, in these methods, the high temperature anneal may complicate the process flow, require additional process chambers for the anneal, fail to create a fully graded region, and/or damage other components in the semiconductor device. Further, this high temperature annealing may diminish film quality and be unable to control the profile of the graded region, limiting profile design and future scaling options for the semiconductor devices. To accommodate this high temperature anneal, some methods include an interface layer disposed between the dielectric and the substrate. The inclusion of an additional interface in the semiconductor devices may increase fixed charges and limit mobility.